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ZILOG
Z86C30/C31/C32/C40 CP96DZ82900
PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION
Z86C30/C31/C32/C40
CMOS Z8(R) CONSUMER CONTROLLER PROCESSOR
FEATURES
Part Z86C30 Z86C31 Z86C32 Z86C40 ROM (KB) 4 2 2 4 RAM* (Byte) 237 125 237 236 Speed (MHz) 16 12 12 16
s
32 Input/Output Lines (C40) 24 Input/Output Lines (C3X) Vectored, Prioritized Interrupts with Programmable Polarity Two Analog Comparators Two Programmable 8-Bit Counter/Timers, Each with Two 6-Bit Programmable Prescaler Watch-Dog Timer/Power-On Reset On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock RAM and ROM Protect
s
* General-Purpose
s s
s
28-Pin DIP, 28-Pin SOIC, 28-Pin PLCC Packages (Z86C3X) 40-Pin DIP, 44-Pin PLCC/QFP Packages (Z86C40) 3.0V to 5.5V Operating Range
s s s s s s
Low-Power Consumption -40C to +105C Operating Range Expanded Register File (ERF)
s
GENERAL DESCRIPTION
The Z86C3X/C40 Consumer Controller Processors (CCP) are members of the Z8 (R) single-chip microcontroller family offering a unique register-to-register architecture that avoids accumulator bottlenecks and offers fast execution of code. Three address spaces (Program Memory, Register File, and Expanded Register File [ERF]), support a wide range of memory configurations. Through the ERF, the designer has access to three additional control registers that provide extra peripheral devices, I/O ports, and register addresses. The rest of the ERF is not physically implemented and is open for future expansion. For applications demanding powerful I/O capabilities, the Z86C3X/C40's dedicated input and output lines are grouped into three and four ports, respectively, and are configurable under software control to provide timing, status signals, or parallel I/O. Two on-chip counter/timers, with a large number of selectable modes, offload the system of administering real-time tasks such as counting/timing and I/O data communications. With ROM/ROMless selectivity, the Z86C40 provides both external memory and pre-programmed ROM, which enables these Z8 microcontrollers to be used in highvolume applications, or where code flexibility is required.
Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS
CP96DZ82900
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GENERAL DESCRIPTION (Continued)
Output Input Vcc GND XTAL /AS /DS R//W /RESET
Port 3
Machine Timing & Instruction Control RESET WDT POR ,
(Only on Z86C40)
Counter/ Timers (2)
ALU
FLAGS Interrupt Control Register Pointer Register File
Prg. Memory 4K
Two Analog Comparators
Program Counter
Port 2
Port 0
Port 1
4 I/O (Bit Programmable)
4
8 Address/Data or I/O (Byte Programmable)
Address or I/O (Nibble Programmable)
(Only on Z86C40)
Functional Block Diagram
2
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Z86C30/C31/C32/C40 CP96DZ82900
PIN DESCRIPTION
28-Pin DIP/SOIC/PLCC Pin Identification
P25 P26 P27 P04 P05 P06 P07 VCC XTAL2 XTAL1 P31 P32 P33 P34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 Z86C30 Z86C31 22 Z86C32 21 20 19 18 17 16 15 P24 P23 P22 P21 P20 P03 GND P02 P01 P00 P30 P36 P37 P35
Pin # 1-3 4-7 8 9
Symbol P27-25 P07-04 VCC XTAL2
Function Port 2, Pins 5,6,7 Port 0, Pins 4,5,6,7 Power Supply Crystal Oscillator Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pins 4,5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pins 0,1,2 Ground, VSS Port 0, Pin 3 Port 2, Pins 0,1,2,3,4
Direction In/Output In/Output Output Input Fixed Input Fixed Output Fixed Output Fixed Output Fixed Input In/Output In/Output In/Output
10 XTAL1 11-13 P33-31 14-15 P35-4 16 P37 17 P36 18 P30 19-21 P02-00 22 GND 23 P03 24-28 P24-20
28-Pin DIP Configuration
P05 XXX P06 XXX P07 XXX VDD XXX XT2 XXX XT1 XXX P31 XXX 5
4
P04 P27 P26
P25 P24 P23 P22
1 26 25 19 18 P21 XXX P20 XXX P03 XXX VSS XXX P02 XXX P01 XXX P00 XXX
P25 P26 P27 P04 P05 P06 P07 VDD XTAL2 XTAL1 P31 P32 P33 P34
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Z86C30 Z86C31 Z86C32
28 27 26 25 24 23 22 21 20 19 18 17 16 15
P24 P23 P22 P21 P20 P03 VSS P02 P01 P00 P30 P36 P37 P35
Z86C30 Z86C31 Z86C32
11 12
P32 P33 P34
28-Pin PLCC Configuration
28-Pin SOIC Configuration
CP96DZ82900
P35 P37 P36 P30
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PIN DESCRIPTION (Continued)
R//W P25 P26 P27 P04 P05 P06 P14 P15 P07 VCC P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 /AS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Z86C40 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 /DS P24 P23 P22 P21 P20 P03 P13 P12 GND P02 P11 P10 P01 P00 P30 P36 P37 P35 /RESET
40-Pin DIP Assignments
40-Pin Dual-In-Line Package Pin Identification Pin # Symbol 1 2-4 5-7 8-9 10 11 12-13 14 15 16-18 19 20 21 R//W P25-27 P04-06 P14-15 P07 VCC P16-17 XTAL2 XTAL1 P31-33 P34 /AS /RESET Function Read/Write Port 2, Pins 5,6,7 Port 0, Pins 4,5,6 Port 1, Pins 4,5 Direction Output In/Output In/Output In/Output Pin # 22 23 24 25 26-27 28-29 30 31 32-33 34 35-39 40 Symbol P35 P37 P36 P30 P00-01 P10-11 P02 GND P12-13 P03 P20-24 /DS Function Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pin 0,1 Port 1, Pin 0,1 Port 0, Pin 2 Ground, GND Port 1, Pin 2,3 Port 0, Pin 3 Port 2, Pin 0,1,2,3,4 Data Strobe Direction Output Output Output Input In/Output In/Output In/Output In/Output In/Output In/Output Output
Port 0, Pin 7 In/Output Power Supply Port 1, Pins 6,7 In/Output Crystal, Oscillator Clock Output Crystal, Oscillator Clock Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe Reset Input Input Output Output Input
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PIN DESCRIPTION (Continued)
GND GND P20 P03 P13 P12 P02 P10 P01 P00 P11
6 P21 P22 P23 P24 /DS N/C R//W P25 P26 P27 P04 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1
44 43 42 41 40 39 38 37 36 35 P30 P36 P37 P35 /RESET R//RL /AS P34 P33 P32 P31
Z86C40
34 33 32 31 30 29
18 19 20 21 22 23 24 25 26 27 28
VCC
VCC
P05
P06
P14
P15
P07
P16
P17
XTAL2
44-Pin PLCC Pin Assignments
44-Pin PLCC Pin Identification Pin # Symbol 1-2 3-4 5 6-10 11 12 13 14-16 17-19 20-21 22 23-24 25-26 27 GND P12-13 P03 P20-24 /DS N/C R//W P25-27 P04-06 P14-15 P07 V CC P16-17 XTAL2 Function Ground, GND Port 1, Pins 2,3 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Data Strobe Not Connected Read/Write Port 2, Pins 5,6,7 Port 0, Pins 4,5,6 Port 1, Pins 4,5 Direction In/Output In/Output In/Output Output Output In/Output In/Output In/Output Pin # Symbol 28 29-31 32 33 34 35 36 37 38 39 XTAL1 P31-33 P34 /AS R//RL /RESET P35 P37 P36 P30 Function Crystal, Oscillator Clock Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe ROM/ROMless Control Reset Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pins 0,1 Port 1, Pins 0,1 Port 0, Pin 2 Direction Input Input Output Output Input Input Output Output Output Input In/Output In/Output In/Output
Port 0, Pin 7 In/Output Power Supply Port 1, Pins 6,7 In/Output Crystal, Oscillator Clock Output
40-41 P00-01 42-43 P10-11 44 P02
CP96DZ82900
XTAL1
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PIN DESCRIPTION (Continued)
GND GND P20 P03 P13 P12 P02 P10 P01 P00
22 21 20 19 18
33 32 31 30 29 28 27 26 25 24 23 P21 P22 P23 P24 /DS N/C R//W P25 P26 P27 P04 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 P30 P36 P37 P35 /RESET R//RL /AS P34 P33 P32 P31
Z86C40
P11
17 16 15 14 13 12
VCC
VCC
P05
P06
P14
P15
P07
P16
P17
XTAL2
44-Pin QFP Pin Assignments
44-Pin QFP Pin Identification Pin # Symbol 1-2 3-4 5 6-7 8-9 10 11 12-14 15 16 17 18 19 20 P05-06 P14-15 P07 VCC P16-17 XTAL2 XTAL1 P31-33 P34 /AS R//RL /RESET P35 P37 Function Port 0, Pins 5,6 Port 1, Pins 4,5 Port 0, Pin 7 Power Supply Port 1 Pins 6,7 Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe ROM/ROMless Control Reset Port 3, Pin 5 Port 3, Pin 7 Direction In/Output In/Output In/Output In/Output Output Input Input Output Output Input Input Output Output Pin # 21 22 23-24 25-26 27 28-29 30-31 32 33-37 38 39 40 41-43 44 Symbol P36 P30 P00-01 P10-11 P02 GND P12-13 P03 P20-24 /DS N/C R//W P25-27 P04 Function Port 3, Pin 6 Port 3, Pin 0 Port 0, Pins 0,1 Port 1, Pins 0,1 Port 0, Pin 2 Ground, GND Port 1, Pins 2,3 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Data Strobe Not Connected Read/Write Port 2, Pins 5,6,7 Port 0, Pin 4 Direction Output Input In/Output In/Output In/Output In/Output In/Output In/Output Output Output In/Output In/Output
XTAL1
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ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature under Bias Storage Temperature Voltage on any Pin with Respect to VSS [Note 1] Voltage on V DD Pin with Respect to VSS Voltage on XTAL1 and /RESET Pins with Respect to VSS [Note 2] Total Power Dissipation Maximum Allowable Current out of VSS Maximum Allowable Current into VDD Maximum Allowable Current into an Input Pin [Note 3] Maximum Allowable Current into an Open-Drain Pin [Note 4] Maximum Allowable Output Current Sinked by Any I/O Pin Maximum Allowable Output Current Sourced by Any I/O Pin
Notes: [1] This applies to all pins except XTAL pins and where otherwise noted. [2] There is no input protection diode from pin to VDD. [3] This excludes XTAL pins. [4] Device pin is not at an output Low state.
Min -40 -65 -0.6 -0.3 -0.6
Max +105 +150 +7 +7 VDD+1 1.21 220 180 +600 +600 25 25
Units C C V V V W mA mA A A mA mA
-600 -600
Notice: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability.
Total power dissipation should not exceed 1.21 W for the package. Power dissipation is calculated as follows: Total Power Dissipation = VDD x [ IDD - (sum of IOH) ] + sum of [ (VDD - VOH) x I OH ] + sum of (V0L x I0L)
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Test Load).
From Output Under T est
150 pF
Test Load Diagram
CAPACITANCE
TA = 25C, VCC = GND = 0V, f = 1.0 MHz; unmeasured pins returned to GND. Parameter Input capacitance Output capacitance I/O capacitance Min 0 0 0 Max 12 pF 12 pF 12 pF
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DC ELECTRICAL CHARACTERISTICS
T A = 0C to +70C Min Max 0.7 VCC 0.7 VCC GND-0.3 GND-0.3 0.7 VCC 0.7 VCC GND-0.3 GND-0.3 VCC-0.4 VCC-0.4 VCC-0.4 VCC-0.4 VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC Typical [1] @ 25C Units 1.3 2.5 0.7 1.5 1.3 2.5 0.7 1.5 3.1 4.8 3.1 4.8 0.3 0.2 0.2 0.1 0.5 0.5 1.5 2.1 1.1 1.7 0.3 0.2 10 10 V V V V V V V V V V V V V V V V V V V V
Sym VCH VCL VIH VIL VOH VOH1 VOL VOL1 VOL2 VRH VRL VOLR
Parameter
VCC Note [3]
Conditions Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator
Notes
Clock Input High Voltage 3.0V 5.5V Clock Input Low Voltage Input High Voltage Input Low Voltage Output High Voltge Low EMI Mode Output High Voltage Output Low Voltage Low EMI Mode Output Low Voltage Output Low Voltage 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.0V 3.0V 5.5V
IOH = - 0.5 mA IOH = - 0.5 mA IOH = - 2.0 mA IOH = - 2.0 mA IOL = 1.0 mA IOL = 1.0 mA IOL = + 4.0 mA IOL = + 4.0 mA IOL = + 6 mA IOL = + 12 mA
[8] [8]
0.6 0.4 0.6 0.4 1.2 1.2 .8 VCC .8 VCC GND-0.3 GND-0.3 VCC VCC 0.2 VCC 0.2 VCC 0.6 0.6
[8] [8] [8] [8] [7] [7] [7] [7] [7] [7]
Reset Input High Voltage 3.0V 5.5V Reset Input Low Voltage 3.0V 5.5V Reset Outut Low Voltage 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
V V mV mV V V A A A A A A mA mA mA mA
IOL = +1.0 mA IOL = +1.0 mA
VOFFSET Comparator Input Offset Voltage VICR Input Common Mode Voltage Range IIL Input Leakage IOL IIR ICC Output Leakage Reset Input Current Supply Current
25 25 GND-0.3 VCC -1.0V GND-0.3 VCC -1.0V -1 2 -1 2 -1 -1 -20 -20 2 2 -130 -180 20 25 15 20
[10] [10] VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC
0.064 0.064 0.114 0.114 -62 -112 7 20 5 15
@ 16 MHz @ 16 MHz @ 12 MHz @ 12 MHz
[4,5] [4,5] [4,5] [4,5]
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DC ELECTRICAL CHARACTERISTICS (Continued)
TA = 0C to +70C Min Max 4.5 8 4 6 3.4 7.0 3 5 8 10 500 800 0.7 1.4 -0.6 -1 3 2.0 2.05 8 15 -5 -8 24 13 2.95 Typical [1] @ 25C Units 2.0 3.7 1.5 3.2 1.5 2.9 1.2 2.5 2 4 310 600 2.4 4.7 -1.8 -3.8 10 4 2.6 mA mA mA mA mA mA mA mA A A A A A A A A mS mS V
Sym ICC1
Parameter Standby Current (Halt Mode)
V CC Note [3] 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
Conditions VIN = 0V, VCC @ 16 MHz VIN = 0V, VCC @ 16 MHz VIN = 0V, VCC @ 12 MHz VIN = 0V, VCC @ 12 MHz Clock Divide by 16 @ 16 MHz Clock Divide by 16 @ 16 MHz Clock Divide by 16 @ 12 MHz Clock Divide by 16 @ 12 MHz VIN = OV, VCC WDT is not Running VIN = OV, VCC WDT is not Running VIN = OV, VCC WDT is Running VIN = OV, VCC WDT is Running OV < VIN < VCC OV < VIN < VCC OV < VIN < VCC OV < VIN < VCC
Notes [4,5] [4,5] [4,5] [4,5] [4,5] [4,5] [4,5] [4,5] [6,11] [6,11] [6,11] [6,11] [9] [9] [9] [9]
ICC2
Standby Current (Stop Mode)
3.0V 5.5V 3.0V 5.5V
IALL IALH
Auto Latch Low Current Auto Latch High Current Power On Reset
3.0V 5.5V 3.0V 5.5V
TPOR VLV
3.0V 5.5V Low Voltage Protection
6 MHz max INT CLK Freq.
[7]
Note: [1] Typicals are at VCC = 5.0V and 3.3V. [2] GND = 0V. [3] The V CC voltage spec. of 3.0V guarantees 3.3V 0.3V and the VDD voltage spec. of 5.5V guarantees 5.0V 0.5V. [4] All outputs unloaded, I/O pins floating, inputs at rail. [5] CL1= CL2 = 10 pF. [6] Same as note [4] except inputs at VCC. [7] Z86C40 only. [8] STD Mode (not Low-EMI Mode). [9] Auto Latch (mask option) selected. [10] For analog comparator inputs when analog comparators are enabled. [11] Clock must be forced Low, when XTAL1 is clock driven and XTAL2 is floating.
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DC ELECTRICAL CHARACTERISTICS
TA=-40C to 105C Min Max 0.7 VCC 0.7 VCC GND-0.3 GND-0.3 0.7 VCC 0.7 VCC GND-0.3 GND-0.3 VCC-0.4 VCC-0.4 VCC-0.4 VCC-0.4 VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC Typical [1] @ 25C Units 1.3 2.5 0.7 1.5 1.3 2.5 0.7 1.5 3.1 4.8 3.1 4.8 0.3 0.2 0.2 0.1 0.5 0.5 1.5 2.1 1.1 1.7 0.4 0.3 10 10 V V V V V V V V V V V V V V V V V V V V
Sym Parameter VCH VCL VIH VIL VOH VOH1 VOL VOL1 VOL2 VRH VRL VOLR
V CC Note [3]
Conditions Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator
Notes
Clock Input High Voltage 3.0V 5.5V Clock Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Low EMI Mode Output High Voltage Output Low Voltage Low EMI Mode Output Low Voltage Output Low Voltage 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.0V 3.0V 5.5V
IOH = - 0.5 mA IOH = - 0.5 mA IOH = - 2.0 mA IOH = - 2.0 mA IOL = 1.0 mA IOL = 1.0 mA IOL = + 4.0 mA IOL = + 4.0 mA IOL = + 6 mA IOL = + 12 mA
[8] [8]
0.6 0.4 0.6 0.4 1.2 1.2 .8 VCC .8 VCC GND-0.3 GND-0.3 VCC VCC 0.2 VCC 0.2 VCC 0.6 0.6 25 25 VCC -1.5V VCC -1.5V 2 2 2 2 -130 -180 20 25 15 20
[8] [8] [8] [8] [7] [7] [7] [7] [7] [7]
Reset Input High Voltage 3.0V 5.5V Reset Input Low Voltage 3.0V 5.5V Reset Output Low Voltage 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
V V mV mV V V A A A A A A mA mA mA mA
IOL = + 1.0 mA IOL = + 1.0 mA
VOFFSET Comparator Input Offset Voltage VICR Input Common Mode Voltage Range IIL Input Leakage IOL IIR ICC Output Leakage Reset Input Current Supply Current
GND-0.3 GND-0.3 -1 -1 -1 -1 -18 -18
[10] [10] VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC
<1 <1 <1 <1 -62 -112 7 20 5 15
@ 16 MHz @ 16 MHz @ 12 MHz @ 12 MHz
[4,5] [4,5] [4,5] [4,5]
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DC ELECTRICAL CHARACTERISTICS (Continued)
T A = -40C Typical [1] to 105C @ Min Max 25C Units 4.5 8 4 6 3.4 7.0 3 5 8 10 600 1000 0.7 1.4 -0.6 -1.0 3.0 2.0 1.8 10 20 -7 -10 25 14 3.3 2.0 3.7 1.5 3.2 1.5 2.9 1.2 2.5 2 4 310 600 2.4 4.7 -1.8 -3.8 7 4 2.6 mA mA mA mA mA mA mA mA A A A A A A A A mS mS V
Sym Parameter ICC1 Standby Current (Halt Mode)
VCC Note [3] 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
Conditions VIN = 0V, VCC @ 16 MHz VIN = 0V, VCC @ 16 MHz VIN = 0V, VCC @ 12 MHz VIN = 0V, VCC @ 12 MHz Clock Divide by 16 @ 16 MHz Clock Divide by 16 @ 16 MHz Clock Divide by 16 @ 12 MHz Clock Divide by 16 @ 12 MHz VIN = OV, VCC WDT is not Running VIN = OV, VCC WDT is not Running VIN = OV, VCC WDT is Running VIN = OV, VCC WDT is Running OV < VIN < VCC OV < VIN < VCC OV < VIN < VCC OV < VIN < VCC
Notes [4,5] [4,5] [4,5] [4,5] [4,5] [4,5] [4,5] [4,5] [6,11] [6,11] [6,11] [6,11] [9] [9] [9] [9]
ICC2
Standby Current (Stop Mode)
3.0V 5.5V 3.0V 5.5V
IALL IALH TPOR VLV
Auto Latch Low Current Auto Latch High Current Power On Reset Low Voltage Protection
3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
4 MHz max INT CLK Freq.
Note: [1] Typicals are at VCC = 5.0V and 3.3V. [2] GND=0V. [3] The V CC voltage spec. of 3.0V guarantees 3.3V 0.3V and the VDD voltage spec. of 5.5V guarantees 5.0V 0.5V. [4] All outputs unloaded, I/O pins floating, inputs at rail. [5] CL1= CL2 = 100pF. [6] Same as note [4] except inputs at VCC. [[7] Z86C40 only. [8] STD Mode (not Low EMI Mode). [9] Auto Latch (mask option) selected. [10] For analog comparator inputs when analog comparators are enabled. [11] Clock must be forced Low, when XTAL1 is clock driven and XTAL2 is floating. [7] Z86C40 only.
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AC CHARACTERISTICS External I/O or Memory Read and Write Timing Diagram (Z86C40 Only)
R//W, /DM
13 12 19
Port 0
16 18 3
20
Port 1
1
A7 - A0
2
D7 - D0 IN
9
/AS
8 4 5 6 11
/DS (Read)
17
10
Port1
A7 - A0
14
D7 - D0 OUT
15 7
/DS (Write)
External I/O or Memory Read/Write Timing (Z86C40 Only)
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AC CHARACTERISTICS External I/O or Memory Read and Write Timing Table (Z86C40 Only)
(SCLK/TCLK = XTAL/2) TA=-40C to 105C TA = -40C to +105C Note [3] 12 MHz 16 MHz 12 MHz 16 MHz VCC Min Max Min Max Min Max Min Max Units 3.0 5.5 3.0 5.5 3.0 5.5 3.0 5.5 3.0 5.5 3.0 5.5 3.0 5.5 3.0 5.5 3.00 5.5 3.0 5.5 3.0 5.5 3.0 5.5 35 35 45 45 250 250 55 55 0 0 200 200 110 110 150 150 0 0 45 55 30 45 45 45 45 45 55 55 45 45 310 310 65 65 35 35 45 45 45 45 45 45 30 30 35 35 35 35 0 0 50 50 35 35 25 25 35 35 25 25 35 35 230 230 65 65 35 35 45 45 45 45 40 40 0 0 135 135 80 80 75 75 0 0 45 55 30 45 45 45 45 45 55 55 45 45 310 310 45 45 30 30 35 35 35 35 25 25 35 35 180 180 55 55 0 0 200 200 110 110 150 150 0 0 50 50 35 55 25 25 35 35 25 25 35 35 230 230 35 35 45 45 250 250 40 40 0 0 135 135 80 80 75 75 25 25 35 35 180 180 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
No Symbol Parameter 1 TdA(AS) 2 TdAS(A) Address Valid to /AS Rise Delay /AS Rise to Address Float Delay
Notes [2] [2] [1,2] [2]
3 TdAS(DR) /AS Rise to Read Data Req'd Valid 4 TwAS /AS Low Width
5 TdAS(DS) Address Float to /DS Fall 6 TwDSR 7 TwDSW /DS (Read) Low Width /DS (Write) Low Width
[1,2] [1,2] [1,2] [2] [2] [2] [2] [2] [2] [2] [1,2] [2] [2]
8 TdDSR(DR) /DS Fall to Read Data Req'd Valid 9 ThDR(DS) Read Data to /DS Rise Hold Time 10 TdDS(A) /DS Rise to Address Active Delay
11 TdDS(AS) /DS Rise to /AS Fall Delay 12 TdR/W(AS) R//W Valid to /AS Rise Delay 13 TdDS(R/W) /DS Rise to R//W Not Valid
3.0 5.5 14 TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay 3.0 5.5 15 TdDS(DW) /DS Rise to Write Data Not Valid Delay 16 TdA(DR) Address Valid to Read Data Req'd Valid 3.0 5.5 3.0 5.5 3.0 5.5 3.0 5.5 3.0 5.5 3.0 5.5
17 TdAS(DS) /AS Rise to /DS Fall Delay 18 TdDM(AS) /DM Valid to /AS Fall Delay 19 TdDS(DM) /DS Rise to DM Valid Delay 20 ThDS(AS) /DS Valid to Address Valid Hold Time
Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] The VCC voltage specification of 3.0V guarantees 3.3V 0.3V, and the VDD voltage specification of 5.5V guarantees 5.0V 0.5V.
Standard Test Load All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. For Standard Mode (not Low-EMI Mode for outputs) with SMR D1 = 0, D0 = 0.
CP96DZ82900
13
ZILOG
Z86C30/C31/C32/C40 CP96DZ82900
AC ELECTRICAL CHARACTERISTICS Additional Timing Diagram
1 3
Clock
2 7 7 2 3
TIN
4 6 5
IRQN
8 9
Clock Setup
11
Stop Mode Recovery Source
10
Additional Timing
14
CP96DZ82900
ZILOG
Z86C30/C31/C32/C40 CP96DZ82900
AC ELECTRICAL CHARACTERISTICS Additional Timing Table (Divide-By-One Mode)
TA = 0C to +70C No Symbol 1 2 3 4 5 6 7 8A 8B 9 10 11 TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin, TfTin TwIL TwIL TwIH Twsm Tost Parameter Input Clock Period Clock Input Rise & Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise & Fall Timer Int. Request Low Time Int. Request Low Time Int. Request Input High Time VCC Note [6] 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 4 MHz Min Max 250 250 DC DC 25 25 T A = 40C to +105C 4 MHz Min Max 250 250 DC DC 25 25 Units ns ns ns ns ns ns ns ns Notes [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] 100 100 100 70 5TpC 5TpC 5TpC 5TpC 12 12 5TpC 5TpC 5TpC 5TpC ns ns ns ns ns ns [1,7,8] [1,7,8] [1,2,7,8] [1,2,7,8] [1,3,7,8] [1,3,7,8] [1,2,7,8] [1,2,7,8] [4,8] [4,8] [4,8,9] [4,8,9]
100 100 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 5TpC 5TpC 12 12
100 100 100 70 5TpC 5TpC 8TpC 8TpC
STOP Mode Recovery Width Spec 3.0V 5.5V Oscillator Start-up Time 3.0V 5.5V
Notes: [1] Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. [2] Interrupt request via Port 3 (P31-P33). [3] Interrupt request via Port 3 (P30). [4] SMR-D5 = 1, POR STOP Mode Delay is on. [5] Reg. WDTMR. [6] The V CC voltage specification of 3.0V guarantees 3.3V 0.3V, and the VDD voltage specification of 5.5V guarantees 5.0V 0.5V. [7] SMR D1 = 0. [8] Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode. [9] For RC and LC oscillator, and for oscillator driven by clock driver.
CP96DZ82900
15
ZILOG
Z86C30/C31/C32/C40 CP96DZ82900
AC ELECTRICAL CHARACTERISTICS Additional Timing Table
T A = -40C to +105C T A = 0C to +70C 16 MHz 12 MHz Min Max Min Max 62.5 62.5 DC DC 15 15 83 83 DC DC 15 15
No Symbol 1 2 3 4 5 6 7 TpC TrC,TfC TwC TwTinL TwTinH TpTin
Parameter Input Clock Period Clock Input Rise & Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise & Fall Timer Int. Request Low Time Int. Request Low Time Int. Request Input High Time
VCC Note [6] 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
Units ns ns ns ns ns ns ns ns
Notes [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8] [1,7,8]
31 31 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 5TpC 5TpC 12 12 5TpC 5TpC 10 5 20 10 40 20 160 80
26 26 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 5TpC 5TpC 12 12 5TpC 5TpC 10 5.0 20 10 40 20 160 80
TrTin, TfTin 8A TwIL 8B TwIL 9 TwIH
ns ns ns ns
[1,7,8] [1,7,8] [1,2,7,8] [1,2,7,8] [1,3,7,8] [1,3,7,8] [1,2,7,8] [1,2,7,8]
10 Twsm 11 Tost 12 Twdt
STOP Mode Recovery Width Spec 3.0V 5.5V Oscillator Start-up Time 3.0V 5.5V Watch-Dog Timer Delay Time Before Refresh 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
ns ns
[4,8] [4,8] [4,8] [4,8] D0 = 0 [5,11] D1 = 0 [5,11] D0 = 1 [5,11] D1 = 0 [5,11] D0 = 0 [5,11] D1 = 1 [5,11] D0 = 1 [5,11] D1 = 1 [5,11]
ms ms ms ms ms ms ms ms
Notes: [1] Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. [2] Interrupt request via Port 3 (P31-P33). [3] Interrupt request via Port 3 (P30). [4] SMR-D5 = 1, POR STOP Mode Delay is on. [5] Reg. WDTMR. [6] The V CC voltage spec. of 3.0V guarantees 3.3V 0.3V and the VDD voltage spec. of 5.5V guarantees 5.0V 0.5V. [7] SMR D1 = 0. [8] Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode. [9] For RC and LC oscillator, and for oscillator driven by clock driver. [10] Standard Mode (not Low EMI output ports). [11] Using internal RC.
16
CP96DZ82900
ZILOG
Z86C30/C31/C32/C40 CP96DZ82900
AC ELECTRICAL CHARACTERISTICS Handshake Timing Diagrams
Data In
Data In Valid
Next Data In Valid
1 3
2
/DAV (Input)
4
Delayed DAV
5
6
RDY (Output)
Delayed RDY
Input Handshake Timing
Data Out
Data Out Valid
Next Data Out Valid
7
/DAV (Output)
8 9 10
Delayed DAV
11
RDY (Input)
Delayed
RDY
Output Handshake Timing
(c) 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com
CP96DZ82900
17

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